Akya is developing a range of application IP, including:
- Geometric Distortion Correction
- Fully synthesisable IP core supporting a wide range of distortion correction for fisheye and other images. Supports high pixel rates (250 Mpixels/s @ 300 MHz) and high resolutions (32 Mpixels and higher)
- Designed for deployment on ASIC/SoC or FPGA (Altera or Xilinx)
- Built on AIPP - the Akya Image Processing Platform
- JPEG encoder
- Highly-configurable JPEG encoder
- Suitable for both ASIC/SoC and FPGA deployment
The core of Akya's technology offering, available to license to suitably-qualified partners.
ART2 consists of:
- ART2 libraries
- Verilog and C++ components
- ART2 development tools
- ART Architecture Compiler (artac)
- Generates Verilog and C++ models of hardware
- ART Assembler (artasm)
- Generates firmware from ART's high-level assembly language
- Support tools
- Linker, memory generator, etc.
ART2 development kit
The ART2 development kit allows users to develop ART hardware and firmware and test its operation using advanced FPGA-based ASIC prototyping techniques.